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1-bit architecture
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#	Item
31	ServerSet III and MXT Technology Sectored Memory Management Indirect "virtual" mapping of main memory Control Bit Field Pointer 0 Pointer 1 Physical Address Minimum Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:38:05 Data types Computer architecture Computer storage media Central processing unit Data structure alignment Pointer SCSI Physical address CPU cache Computing Computer memory Information
32	LPC15xx 32-bit ARM Cortex-M3 microcontroller; up to 256 kB flash and 36 kB SRAM; FS USB, CAN, RTC, SPI, USART, I2C Rev. 1 — 19 February[removed]Product data sheet Add to Reading List Source URL: www.nxp.com Language: English - Date: 2014-06-27 07:32:25 Computer hardware ARM architecture Instruction set architectures Mbed microcontroller ARM Cortex-M Quad Flat Package I²C NXP Semiconductors EFM32 Microcontrollers Computer architecture Electronics
33	LPC11E6x 32-bit ARM Cortex-M0+ microcontroller; up to 256 kB flash and 36 kB SRAM; 4 kB EEPROM; 12-bit ADC Rev. 1.2 — 21 May[removed]Product data sheet Add to Reading List Source URL: www.nxp.com Language: English - Date: 2014-05-21 13:02:20 Microcontrollers Embedded systems Instruction set architectures ARM architecture Integrated circuits I²C Joint Test Action Group General Purpose Input/Output ARM Cortex-M Computer architecture Electronics Electronic engineering
34	System V Application Binary Interface AMD64 Architecture Processor Supplement Draft Version[removed]Edited by Michael Matz , Jan Hubiˇcka2 , Andreas Jaeger3 , Mark Mitchell4 1 Add to Reading List Source URL: uclibc.org Language: English - Date: 2015-03-06 01:20:02 X86 architecture Subroutines X86-64 Application binary interface Central processing unit 64-bit X86 Calling convention Fortran Computing Computer architecture Software engineering
35	Hot Chips IA64 Tutorial, part 1 Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:48:57 Instruction set architectures Itanium Branch predication Reduced instruction set computing Very long instruction word Intel 64-bit Compiler Microprocessor Computer architecture Computing Computer hardware
36	PA-RISC 2.0 Firmware Architecture Reference Specification Version 1.0 Printed in U.S.A. August 22, 2001 Add to Reading List Source URL: ftp.parisc-linux.org Language: English - Date: 2001-09-04 11:38:08 Instruction set architectures Subroutines Source code Assembly languages Calling convention Pointer Addressing mode 64-bit Reduced instruction set computing Computing Computer programming Software engineering
37	HC17.S4T1 Telairity-1 A Real Time H.264 High Definition Video Architecture.ppt Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:46:07 Computer hardware 64-bit CPU cache Instruction set Scalar processor CDC Cyber Comparison of CPU architectures Computer architecture Computing Central processing unit
38	IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING (TDSC) 1 Using Register Lifetime Predictions to Protect Register Files Against Soft Errors Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-29 19:16:16 Central processing unit Computer memory Register renaming CPU cache Register file Branch predictor Parity bit Processor register 64-bit Computer architecture Computer hardware Computing
39	Microsoft Word - DS1921G ordering info Add to Reading List Source URL: datasheets.maximintegrated.com Language: English - Date: 2015-04-01 12:44:17 Microcontrollers Electronics 64-bit Instruction set architectures Computer architecture Computer hardware 1-Wire
40	Microsoft Word - NGN_Access_Planning-_Report-2[1] FINAL Nov 2009.docx Add to Reading List Source URL: www.itu.int Language: English - Date: 2010-12-21 04:39:50 Technology Network architecture Next-generation network Telecommunications systems Very-high-bit-rate digital subscriber line G.992.5 Asymmetric digital subscriber line Public switched telephone network IPTV Digital subscriber line Electronics Electronic engineering

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